The electronic circuit of an integrated circuit (IC) can be considered to be a graph of connected components such as, but not limited to, transistors and resistors. Such an entity is commonly referred it as a netlist. Each component is mapped to one or more layout objects that are geometrical 2-dimensional objects such as, but not limited to, rectangles, polygons, and paths. In turn, these layout objects are used to define regions within the semiconductor die, which will receive different processing steps such as dopant, implants to produce N-type or P-type regions during the integrated circuit fabrication process.
Every layout object must satisfy manufacturing rules that specify geometrical requirements for each object as well as the relationship of an object to other objects. The manufacturing rules increase the probability that the final IC products will meet product specifications. Examples of such requirements include, but are not limited to, such items as minimum layout object width and minimum spacing from one layout object to that of another.
Ultimately, every IC netlist must be mapped to a layout representation prior to its manufacture. One important goal is minimize the layout area for an IC circuit since it has a direct impact on the eventual product cost while abiding with manufacturing rules.
Design engineers typically use electronic design automation (“EDA”) applications to create IC layouts. These applications provide sets of computer-based tools for creating, editing, and analyzing IC design layouts.
EDA applications create layouts from an IC netlist by various operations. Some, but not all, of the physical design (“PD”) operations need to transform a netlist to a layout include: (1) placement which specifies the location of the IC components; (2) routing which generates the layout objects used to connect the IC components; (3) addition operations to complete the layout such as, but not limited to adding substrate/well contacts and power/ground routing. The result of the physical design process is an IC layout.
The PD procedure is a very difficult and complicated sequence of processes. The procedure is such a difficult computational problem that a successful generation of an IC layout is not always assured. If any of the steps in a PD process fails, then an IC layout cannot be generated. The procedure is made more onerous since IC manufacturing rules have become very complex and extremely difficult to incorporate into the typical PD without negatively impacting the probability that the PD can successfully generate an IC layout.